1. Field of the Invention
The present invention relates to a fringe field switching (FFS) mode liquid crystal display (LCD) device, and more particularly, to an array substrate for an FFS mode LCD device capable of improving transmittance and aperture ratio and an FFS mode LCD device including the array substrate. The FFS mode LCD device can display a high quality image.
2. Discussion of the Related Art
A related art liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite alignment direction as a result of their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by application of an electric field across the liquid crystal molecules. As the intensity or direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Since incident light is refracted based on the orientation of the liquid crystal molecules due to the optical anisotropy of the liquid crystal molecules, images can be displayed by controlling light transmissivity.
Since the LCD device including a thin film transistor (TFT) as a switching element, referred to as an active matrix LCD (AM-LCD) device, has excellent characteristics such as high resolution and display of moving images, the AM-LCD device has been widely used.
The AM-LCD device includes an array substrate, a color filter substrate and a liquid crystal layer interposed therebetween. The array substrate may include a pixel electrode and TFT, and the color filter substrate may include a color filter layer and a common electrode. The AM-LCD device is driven by an electric field between the pixel electrode and the common electrode resulting in excellent properties of transmittance and aperture ratio. However, since the AM-LCD device uses a vertical electric field, the AM-LCD device has a bad viewing angle.
An in-plane switching (IPS) mode LCD device may be used to resolve the above-mentioned limitations. FIG. 1 is a cross-sectional view of the related art IPS mode LCD device. As shown in FIG. 1, the array substrate and the color filter substrate are separated and face each other. The array substrate includes a first substrate 10, a common electrode 17 and a pixel electrode 30. Though not shown, the array substrate may include a TFT, a gate line, a data line, for example. The color filter substrate includes a second substrate 9, a color filter layer (not shown), for example. A liquid crystal layer 11 is interposed between the first substrate 10 and the second substrate 9. Since the common electrode 17 and the pixel electrode are formed on the first substrate 10 on the same level, a horizontal electric field “L” is generated between the common and pixel electrodes 17 and 30.
FIGS. 2A and 2B are cross-sectional views showing turned on/off conditions of the related art IPS mode LCD device. As shown in FIG. 2A, when the voltage is applied to the IPS mode LCD device, liquid crystal molecules 11a above the common electrode 17 and the pixel electrode 30 are unchanged. But, liquid crystal molecules 11b between the common electrode 17 and the pixel electrode 30 are horizontally arranged due to the horizontal electric field “L”. Since the liquid crystal molecules are arranged by the horizontal electric field, the IPS mode LCD device has a characteristic of a wide viewing angle. FIG. 2B shows a condition when the voltage is not applied to the IPS mode LCD device. Because an electric field is not generated between the common and pixel electrodes 17 and 30, the arrangement of liquid crystal molecules 11 is not changed. However, the IPS mode LCD device has poor aperture ratio and transmittance.
A fringe field switching (FFS) mode LCD device has been introduced to resolve the above-mentioned limitations. In the FFS mode LCD device, the liquid crystal molecules are driven by a fringe field.
FIG. 3 is a plan view of an array substrate for the related art FFS mode LCD device. As shown in FIG. 3, an array substrate includes a substrate 41, a gate line 43, a data line 51, a thin film transistor (TFT) “Tr”, a common electrode 75 and a pixel electrode 60. The gate line 43 and the data line 51 are formed on the substrate 41 and cross each other to define a pixel region “P”. The gate line 43 is insulated from the data line 51 due to a gate insulating layer (not shown). The TFT “Tr” is formed in each pixel region “P” and connected to the gate and data lines 43 and 51. The TFT “Tr” includes a gate electrode 45, the gate insulating layer, a semiconductor layer (not shown), a source electrode 55 and a drain electrode 58. The gate electrode 45 is connected to the gate line 43, and the source electrode 55 is connected to the data line 51.
The pixel electrode 60 is formed in each pixel region “P”. The pixel electrode 60 is electrically connected to the drain electrode 58 of the TFT “Tr” through a drain contact hole 59. The pixel electrode 60 has a plate shape and includes a plurality of openings “op”. Each of the openings “op” has a bar shape. In addition, the common electrode 75 having a plate shape is formed on an entire surface of a display region of the substrate 41. The common electrode 75 overlaps the pixel electrode 60. Although the common electrode 75 is formed on an entire surface of the display region of the substrate 41, the common electrode 75 corresponding to one pixel region “P” is marked by a dot-line.
In the array substrate for the FFS mode LCD device having the above structure, when voltages are applied to the common electrode 75 and the pixel electrodes 60, a fringe field is induced between the pixel and common electrodes 60 and 75.
In the above array substrate for the FFS mode LCD device, the openings “op” of the pixel electrode 60 perfectly overlaps the common electrode 75. In this case, an uniform electric field is not generated at both end portions of the opening “op” along a major axis of the opening “op”. The end portions, where non-uniform electric field is generated, may be referred to as a disclination area “DA”. Namely, the liquid crystal molecules in the disclination area “DA” have non-uniform arrangements. Since the FFS mode LCD device has a less transmittance in the disclination area “DA” than other areas with an ON state, there are dark images in the disclination area “DA”, as shown in FIG. 4 showing a picture showing a pixel region of an array substrate for the related art FFS mode LCD device.
The FFS mode LCD device has a decrease of transmittance and displaying quality due to the disclination area.
FIG. 5 is a plan view of the related art FFS mode LCD device. As shown in FIG. 5, the FFS mode LCD device 40 includes a first substrate 42, a second substrate (not shown) and a liquid crystal layer (not shown) interposed therebetween.
On the first substrate 42, a gate line 44, a data line 52, a thin film transistor (TFT) “Tr”, a common electrode 76 and a pixel electrode 61 are formed. The gate line 44 and the data line 52 are formed on the first substrate 42 and cross each other to define a pixel region “P”. The gate line 44 is insulated from the data line 52 due to a gate insulating layer (not shown). The TFT “Tr” is formed in each pixel region “P” and connected to the gate and data lines 44 and 52. The TFT “Tr” includes a gate electrode 46, the gate insulating layer, a semiconductor layer (not shown), a source electrode 56 and a drain electrode 59. The gate electrode 46 is connected to the gate line 44, and the source electrode 56 is connected to the data line 52.
The pixel electrode 61 is formed in each pixel region “P”. The pixel electrode 61 is electrically connected to the drain electrode 59 of the TFT “Tr”. The pixel electrode 61 has a plate shape and includes a plurality of openings “op”. Each of the openings “op” has a bar shape. The pixel electrode 61 is disposed inside of the pixel region “P”. Namely, the pixel electrode 61 does not overlap the gate and data lines 44 and 52 and is spaced apart from the gate and data lines 44 and 52 by a predetermined distance. The reason why the pixel electrode does not overlap the gate and data lines 44 and 52 is that there is a parasitic capacitance between the gate line 44 the pixel electrode 61 and between the data line 52 and the pixel electrode 61 such that a distortion in an electrical field is generated when the pixel electrode overlaps the gate and data lines 44 and 52 with the gate insulating layer (not shown) therebetween. Accordingly, to prevent these problems, the pixel electrode does not overlap the gate and data lines 44 and 52.
In addition, the common electrode 76 having a plate shape is formed on an entire surface of a display region of the first substrate 42. The common electrode 76 overlaps the pixel electrode 61. Although the common electrode 76 is formed on an entire surface of the display region of the first substrate 42, the common electrode 76 corresponding to one pixel region “P” is marked by a dot-line. The first substrate 42, where the gate line 44, the data line 52, the TFT “Tr”, the pixel electrode 61 and the common electrode 76 are formed, may be referred to as an array substrate.
In the array substrate for the FFS mode LCD device having the above structure, when voltages are applied to the common electrode 76 and the pixel electrodes 61, a fringe field is induced between the pixel and common electrodes 61 and 76.
On the second substrate (not shown) facing the first substrate 42, a color filter layer (not shown) and a black matrix 85 are formed. The color filter layer includes color filter patterns of red, green and blue colors. The color filter patterns correspond to the pixel region “P”. The black matrix 85 is disposed to correspond to boundaries of the pixel region “P”. Namely, the black matrix 85 corresponds to the gate line 44, the data line 52 and the TFT “Tr”.
In the above array substrate for the FFS mode LCD device, the openings “op” of the pixel electrode 60 perfectly overlaps the common electrode 75. In this case, an uniform electric field is not generated at both end portions of the opening “op” along a major axis of the opening “op”. The end portions, where non-uniform electric field is generated, may be referred to as a disclination area “DA”. Namely, the liquid crystal molecules in the disclination area “DA” have non-uniform arrangements. Since the FFS mode LCD device has a less transmittance in the disclination area “DA” than other areas with an ON state, there are dark images in the disclination area “DA”.
Since light is abnormally transmitted in the disclination area “DA”, there is a decrease of displaying quality. Accordingly, the black matrix 85 extends to shield the disclination area “DA”. When the black matrix 85 has wider area, there is a decrease in aperture ratio and transmittance.